(a) Field of the Invention
The invention relates to a frequency/phase recovery circuit, particularly a digital frequency/phase recovery circuit in which the frequencies of multi-phase reference clocks are identical to the frequency of an input signal, and the phase of the input signal determines which multi-phase reference clock is to be selected as an output clock.
(b) Description of the Related Art
In the process of transmitting signals, when the channel bandwidth is lower than the bandwidth of the signals transmitted in the channel, inter-symbol interference (ISI) may occur in adjacent bits of the signals. In order to mitigate the inter-symbol interference (ISI), a signal processing technique called partial response maximum likelihood (PRML) is widely used. However, when such technique is applied, the input signal must be accurately sampled in order to generate data correctly.
FIG. 1 shows a block diagram illustrating the architecture of the PRML signal processing used to read out data such as recorded information on a disc. Referring to FIG. 1, the architecture includes an analog to digital converter (ADC) 12, an adaptive equalizer 13, a Viterbi decoder 14, and a timing recovery circuit 15. The ADC 12 receives an input signal, such as a radio frequency (RF) signal read out from a disc, and samples the input signal according to a sampling clock to generate a sampled signal. The adaptive equalizer 13 receives the sampled signal and generates an equalization signal, and the Viterbi decoder 14 decodes the equalization signal to produce an associated output signal. The timing recovery circuit 15 generates the sampling clock for the ADC 12 according to the input signal, so that the ADC 12 is able to correctly sample the input signal at a proper sampling point. The architectures of the adaptive equalizer 13 and the Viterbi decoder 14 belong to conventional arts, thus not to be explained in detail.
However, the phase of the sampling clock generated by the timing recovery circuit 15 may fail to be picked at the best sampling point, then this may result in a sampling error for the ADC 12 to cause the Viterbi decoder 14 to incorrectly decode the equalization signal.
The example references regarding the typical PRML technique are listed below:    1. Kurt H. Mueller, Markus Muller, “Timing recovery in digital Synchronous data receivers”, IEEE Trans. on Comms., Vol., com-24, No. 5, May 1976, pp. 516-531. The reference discloses an algorithm where the sampling frequency is given as 1/T; however, the algorithm achieves only phase synchronization but without frequency synchronization.    2. Alexander Taratorin, “Characterization of Magnetic Recording Systems”, pp. 187-188. The disclosed system generates a sampling clock by means of a signal-slope technique where the sampling frequency must be higher than 1/T to acquire a slope signal, and hence the consuming power of the ADC is considerable and its design architecture is complicated. Further, the disclosed system achieves only phase synchronization but without frequency synchronization.    3. F. M. Gardner, “ABPSK/QPSK Timing Error Detector for Sampled Receiver”, IEEE Trans. On Comms., vol. COM-34, May 1986, pp. 423429. The reference discloses a detector algorithm where the sampling frequency is given as 2/T, so that the consuming power of the ADC is considerable and its design architecture is complicated. Further, the detector algorithm achieves only phase synchronization but without frequency synchronization.
However, a phase-looked loop commonly used in the above PRML techniques to achieve frequency synchronization is not fully digitalized. Hence, the consuming power fails to go down, and the benefit of power reduction cannot be achieved even if the fabrication processes are improved.